Memory device and associated flash memory controller

ABSTRACT

The present invention provides a memory device including a connector and a flash memory controller. The connector is configured to connect to a first host and a second host. The flash memory controller is configured to select one of the first host and the second host based on a selection signal, and the flash memory controller only processes commands from the selected one of the first host and the second host, and accesses a flash memory module based on the commands.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation of the co-pending U.S. application Ser. No.16/796,839 (filed on Feb. 20, 2020). The entire content of the relatedapplications is incorporated herein by reference.

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention relates to a memory device, and more particularly,to a failover mechanism of a memory device.

2. Description of the Prior Art

A solid-state drive (SSD) is a memory device that uses integratedcircuit assemblies to store data, and the SSD becomes popular in theenterprise applications such as data center. In order to provide higheravailability for the enterprise applications, the system generally has afailover mechanism that allows two hosts or two servers to access theSSD, that is if the primary server fails to access the SSD due to theoperating system (OS) crash or hard disk broken issue, the standbyserver can immediately replace the primary server to avoid serviceinterruption.

The conventional failover mechanism uses a dual-port SSD that allows twoservers to concurrently access, however, the dual-port SSD has two flashmemory controllers inside, and is very expensive. Therefore, in order tolower the manufacturing cost, a single-port SSD with a PeripheralComponent Interconnect Express (PCIe) switch may be used to replace thefunctions of the dual-port SSD, however, the PCIe switch is alsoexpensive, and a size of the PCIe switch is too large to fit inside thesingle-port SSD. Therefore, how to provide the failover mechanism usingthe single-port SSD is an important topic.

SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provide afailover mechanism for the single-port SSD, and the single-port SSDitself does not have PCIe switch for communicating with two hosts, tosolve the above-mentioned problems.

According to one embodiment of the present invention, a memory deviceincluding a connector and a flash memory controller is provided. Theconnector is configured to connect to a first host and a second host.The flash memory controller is configured to select one of the firsthost and the second host based on a selection signal, and the flashmemory controller only processes commands from the selected one of thefirst host and the second host, and accesses a flash memory module basedon the commands.

According to another embodiment of the present invention, a flash memorycontroller is disclosed, wherein the flash memory controller isconfigured to access a flash memory module, and the flash memorycontroller comprises a memory for storing a program code, and amicroprocessor for executing the program code to access the flash memorymodule via a control logic circuit. The flash memory controller iscoupled to a first host and a second host, the microprocessor receives aselection signal indicating which one of the first host and the secondhost is selected, and the microprocessor only processes commands fromthe selected one of the first host and the second host, and accessing aflash memory module based on the commands.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating a system according to one embodiment ofthe present invention.

FIG. 2 shows a failover process of the system according to oneembodiment of the present invention.

FIG. 3 is a flowchart of a failover process of the system according toone embodiment of the present invention.

FIG. 4 is a diagram illustrating a flash memory controller according toone embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 1 is a diagram illustrating a system 100 according to oneembodiment of the present invention. As shown in FIG. 1, the system 100comprises two hosts 110 and 120, a memory device such as a SSD 130 and abackplane 140. The host 110 comprising at least a PCIe switch 112 and abaseboard management controller (BMC) 118, and the PCIe switch 112comprises an upstream port 114 and a plurality of downstream ports (inthis embodiment, the PCIe switch 112 comprises three downstream ports116_1-116_3), wherein the upstream port 114 is used to connect aprocessing circuit such as a central processing unit (CPU) within thehost 110, and each of the downstream ports 116_1-116_3 is used toconnect to a device external to the host 110. The host 120 comprises atleast a PCIe switch 122 and a BMC 128, and the PCIe switch 122 comprisesan upstream port 124 and a plurality of downstream ports (in thisembodiment, the PCIe switch 122 comprises three downstream ports126_1-126_3), wherein the upstream port 124 is used to connect aprocessing circuit such as a CPU within the host 120, and each of thedownstream ports 126_1-126_3 is used to connect to a device external tothe host 120. The SSD 130 comprises a flash memory controller 132, amultiplexer 134, a logical circuit 136, a connector 138 and a flashmemory module 139. The backplane 140 comprises an input/output (IO)expander. In this embodiment, the system 110 may be applied to a datacenter, that is the SSD 130 is configured to store and output data vialocal area network or Internet, and one of the hosts 110 and 120 is usedto access the SSD 130 via the backplane.

In this embodiment, the connector 138 of the SSD 130 is a “8639connector” or a “U.2 connector” comprising four lanes, and two of thelanes (e.g. lane #0 and lane #1) are coupled to the downstream port116_1 of the host 110, and the other two lanes (e.g. lane #2 and lane#3) are coupled to the downstream port 126_1 of the host 120. The SSD130 is a single-port SSD, that is the SSD 130 has only one flash memorycontroller 132, and only the flash memory controller 132 is allowed toreceive the commands (e.g. read command or write command) from the host110/120 to access the flash memory module 139. It is noted that flashmemory controller 132 may be a single package mounted on a printedcircuit board (PCB) within the SSD 130, and this single packagecomprises only one die for accessing the flash memory module 139. Inother words, in the SSD 130 serving as the single-port SSD, the SSD 130cannot be accessed by the hosts 110 and 120 simultaneously, that is theSSD 130 only receives commands from one host 110/120 at a time. In thisembodiment, the flash memory controller 132 is configured to use onlytwo of the four lanes to communicate with the host 110/120 at the sametime, for example, the flash memory controller 132 is configured to usethe signal/data of the lane #0 and the lane #1 of the connector 138.

In the operations of the system 100, suppose that the host 110 is activedevice that is accessing the SSD 130 and the host 120 is a standbydevice that is not able to access the SSD 130, the BMC 118 is configuredto control the 10 expander 142 to generate a selection signal SEL to themultiplexer 134 and the flash memory controller 132. At this time, thehost 110 generates a reference clock signal RefClk #0 and a reset signalPERst #0, and the multiplexer 134 refers to the selection signal SEL toselect the reference clock signal RefClk #0 as an output reference clocksignal RefClk, and the flash memory controller 132 uses the outputreference clock signal RefClk to execute the operations; and the flashmemory controller 132 further receives the reset signal PERst #0 via thelogical circuit 136 to reset the internal configuration. In addition,the flash memory controller 132 further receives the selection signalSEL from the multiplexer 134 to know that which one of the hosts 110 and120 is active, for the flash memory controller 132 to have theappropriate configurations. It is noted that the host 120 (standbydevice) does not generate a reference clock signal RefClk #1 and a resetsignal PERst #1. After the configuration of the flash memory controller132 is reset, the CPU of the host 110 can send the commands to the flashmemory controller 132 via the upstream port 114 and downstream port116_1 of the PCIe switch 112 and the connector 138, and the flash memorycontroller 132 refers to the commands from the host 110 to access theflash memory module 139. At this time, because the flash memorycontroller 132 is configured to use only the lane #0 and the lane #1 tocommunicate with the host 110, the lane #2 and the lane #3 are disabled(that is the flash memory controller 132 does not process the signalscorresponding to the lane #2 and the lane #3).

In the embodiment shown in FIG. 1, if the host 110 suddenly fails toaccess the SSD 130, for example, the operating system of the host 110crashes, a hard-disk within the host 110 is broken, the downstream port116_1 is disabled, or any other failure causes, the system 100 canimmediately execute the failover mechanism, that is the host 120replaces the host 110. Specifically, referring to FIG. 2, because thehosts 110 and 120 always communicate with each other, the host 120 candetect if the host 110 is able to access the SSD 130, for example, ifthe host 120 receives a special signal indicating a failover commandfrom the host 110, and/or the host 120 does not receive a signal that isperiodically sent from the host 110, and/or the host 120 sends a signalto the host 110 but does not receive a response, or any other failuredetection mechanism, the host 120 can determine that the host 110 failsto access the SSD 130. Once the host 120 determines that the host 110fails to access the SSD 130, the CPU of the host 120 notifies the BMC128 to communicate with the BMC 118 to try to disable the downstreamport 116_1 of the PCIe switch 112, and the CPU of the host 120 notifiesthe BMC 128 to control the 10 expander 142 to generate the selectionsignal SEL, which indicates that the host 120 is selected, to themultiplexer 134 and the flash memory controller 132. At this time, thehost 120 generates the reference clock signal RefClk #1 and the resetsignal PERst #1, and the multiplexer 134 refers to the selection signalSEL to select the reference clock signal RefClk #1 as the outputreference clock signal RefClk, and the flash memory controller 132 usesthe output reference clock signal RefClk to executes the operations; andthe flash memory controller 132 further receives the reset signal PERst#1 via the logical circuit 136 to reset the internal configuration. Inaddition, the flash memory controller 132 further receives the selectionsignal SEL from the multiplexer 134 to know that the host 120 becomesthe active device and the host 110 becomes the standby device, for theflash memory controller 132 to have the appropriate configurations. Itis noted that the host 110 (standby device) may not generate thereference clock signal RefClk #0 and the reset signal PERst #0. Afterthe downstream port 116_1 of the PCIe switch 112 is disabled, the host120 enables the downstream port 126_1 of the PCIe switch 122. It isnoted that, because the flash memory controller 132 is configured toonly use lane #0 and lane #1 of the connector 138, and the host 120originally corresponds to the lane #2 and the lane #3 of the connector138, the flash memory controller 132 may perform a lane reversaloperation to communicate to the host 120 successfully. That is, the pinscorresponding to the original lane #0 in the connector 138 areconfigured to be corresponding to the lane #3, the pins corresponding tothe original lane #1 in the connector 138 are configured to becorresponding to the lane #2, the pins corresponding to the originallane #2 in the connector 138 are configured to be corresponding to thelane #1, and the pins corresponding to the original lane #3 in theconnector 138 are configured to be corresponding to the lane #0. Inaddition, the lanes of the downstream port 126_1 of the PCIe switch 122are configured to correspond the lanes of the connector 138, forexample, the PCIe switch 122 may send training signals to the flashmemory controller 132 to determine if the lanes are matched, if thelanes are not matched, the PCIe switch 122 may also execute the lanereversal operation to make that the pins corresponding to the originallane #0 in the downstream port 126_1 are configured to be correspondingto the lane #1, and the pins corresponding to the original lane #1 inthe downstream port 126_1 are configured to be corresponding to the lane#0. After the configuration of the flash memory controller 132 and thePCIe switch 122 is reset, the CPU of the host 120 can send the commandsto the flash memory controller 132 via the upstream port 124 anddownstream port 126_1 of the PCIe switch 122 and the connector 138, andthe flash memory controller 132 refers to the commands from the host 120to access the flash memory module 139.

In addition, because the flash memory controller 132 is alwaysconfigured to use only the lane #0 and the lane #1 to communicate withthe host 110/120, the other lanes such as the lane #2 and the lane #3should be controlled to be disabled to avoid incorrect operations of theSSD 130. In one embodiment, the lane #2 and the lane #3 may be disabledby the host 110/120. In another embodiment, the lane #2 and the lane #3may be disabled by the flash memory controller 132, for example, if theflash memory controller 132 receives the selection signal SEL indicatingthat the host 110 is active, and the lanes are configured as shown inFIG. 1, the flash memory controller 132 directly enables the lane #0 andthe lane #1 and disables the lane #2 and the lane #3; and if the flashmemory controller 132 receives the selection signal SEL indicating thatthe host 120 is active and the lanes are originally configured as shownin FIG. 1, the flash memory controller 132 firstly performs the lanereversal operation to configure the lanes as shown in FIG. 2, and thenenables the lane #0 and the lane #1 and disables the lane #2 and thelane #3 after the lane reversal operation is done.

In light of above, by adding the multiplexer 134 and designing the flashmemory controller 132 to have the above-mentioned failover mechanism,system 100 can simply use the SSD 130 (single-port SSD) to achieve thehigh availability purposes, and the SSD 130 does not have any PCIeswitch inside. Therefore, the SSD 130 within the system 100 of theembodiment has higher availability and lower manufacturing cost.

FIG. 3 is a flowchart of a failover process of the system 100 accordingto one embodiment of the present invention. Referring to theabove-mentioned embodiments, the flow is described as follows.

Step 300: the flow starts.

Step 302: a first host serves as an active device and a second hostserves as a standby device, and the first host accesses a SSD.

Step 304: the second host determines that the first host is unable toaccess the SSD, and the second host disables the downstream port of thefirst host.

Step 306: the second host controls the SSD to use a reference clock fromthe second host.

Step 308: the second host transmits a reset signal to reset a flashmemory controller of the SSD.

Step 310: the second host enables the downstream port of the PCIeswitch, and starts to access the SSD.

FIG. 4 is a diagram illustrating the flash memory controller 132according to one embodiment of the present invention. As shown in FIG.1, the flash memory controller 132 may comprise a processing circuitsuch as a microprocessor 412, a storage unit such as a read-only memory(ROM) 412M, a control logic circuit 414, a random-access memory (RAM)416, and a transmission interface circuit 418, where the abovecomponents may be coupled to one another via a bus. The RAM 416 isimplemented by a Static RAM (SRAM), but the present invention is notlimited thereto. The RAM 416 may be arranged to provide the flash memorycontroller 132 with internal storage space. For example, the RAM 416 maybe utilized as a buffer memory for buffering data. In addition, the ROM412M of this embodiment is arranged to store a program code 412C, andthe microprocessor 412 is arranged to execute the program code 412C tocontrol the access of the flash memory 139. Note that, in some examples,the program code 412C may be stored in the RAM 416 or any type ofmemory. Further, the control logic circuit 414 may be arranged tocontrol the flash memory module 139, and may comprise an encoder 432, adecoder 434, a randomizer 436, a de-randomizer 438 and other circuits.The transmission interface circuit 418 may conform to a specificcommunications specification (e.g. Serial Advanced Technology Attachment(Serial ATA, or SATA) specification, Peripheral Component Interconnect(PCI) specification, PCIe specification, UFS specification, etc.), andmay perform communications according to the specific communicationsspecification, for example, perform communications with the host 110/120via the connector 138.

In this embodiment, because the SSD 130 comprises only one flash memorycontroller 132 comprising the elements as shown in FIG. 4, all of thecommands or data communicated between the host 110/120 and the flashmemory module 139 must be processed via the elements controlled by themicroprocessor 142 shown in FIG. 4, and all of the regions of the flashmemory module 139 are configured to be accessed by the single flashmemory controller 132.

Briefly summarized, in the system of the present invention, by providingthe multiplexer within the SSD and designing the flash memory controllerto have the above-mentioned failover mechanism, the system can simplyuse the single-port SSD to achieve the high availability purposes, andthe SSD does not have any PCIe switch inside. Therefore, the SSD withinthe system 100 has higher availability and lower manufacturing cost.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

What is claimed is:
 1. A memory device, comprising: a connector,configured to connect to a first host and a second host; a flash memorycontroller, for selecting one of the first host and the second hostbased on a selection signal, and only processing commands from theselected one of the first host and the second host, and accessing aflash memory module based on the commands; wherein the memory device isa single-port solid-state drive (SSD), and the first host and the secondhost are not allowed to access the flash memory module via the flashmemory controller at a same time; wherein the connector is configured tohave a plurality of lanes, a first portion of the lanes correspond tothe first host, a second portion of the lanes correspond to the secondhost; and if the first host is selected, the first portion of the lanesare enabled, and the second portion of the lanes are not used by theflash memory controller to communicate with the first host; and if thesecond host is selected, the second portion of the lanes are enabled,and the first portion of the lanes are not used by the flash memorycontroller to communicate with the first host.
 2. The memory device ofclaim 1, wherein initially the first host communicates with the flashmemory controller, and when the flash memory controller receives theselection signal indicating that the second host is selected, the flashmemory controller executes a lane reversal operation to reverse lanenumbers of the lanes, and second portion of the lanes are enabled, andthe first portion of the lanes are disabled.
 3. The memory device ofclaim 2, wherein when the flash memory controller receives the selectionsignal indicating that the second host is selected, the flash memorycontroller executes the lane reversal operation to reverse the lanenumbers of the lanes, and the flash memory controller enables the secondportion of the lanes, and disables the first portion of the lanes. 4.The memory device of claim 1, wherein initially the first hostcommunicates with the flash memory controller, and when the flash memorycontroller receives the selection signal indicating that the second hostis selected, the flash memory controller receives a reference clocksignal from the second host, and the flash memory controller isconfigured to process the commands from the second host, and stopprocessing the commands from the first host.
 5. The memory device ofclaim 4, further comprising: a multiplexer, for selecting one of a firstreference clock signal and a second reference clock signal as thereference clock signal according to the selection signal, wherein thefirst reference clock signal corresponds to the first host, and thesecond reference clock signal corresponds to the second host; whereinthe when the flash memory controller receives the selection signalindicating that the second host is selected, the multiplexer selects thesecond reference clock signal as the reference clock signal, and outputsthe reference clock signal to the flash memory controller.
 6. A flashmemory controller, wherein the flash memory controller is configured toaccess a flash memory module, the flash memory controller is built in asingle-port solid-state drive (SSD), and the flash memory controllercomprising: a memory, for storing a program code; and a microprocessor,for executing the program code to access the flash memory module via acontrol logic circuit; wherein the flash memory controller is coupled toa first host and a second host, the microprocessor receives a selectionsignal indicating which one of the first host and the second host isselected, and the microprocessor only processes commands from theselected one of the first host and the second host, and accessing aflash memory module based on the commands; and the microcontroller isnot allowed to process the commands from the first host and the secondhost at a same time; wherein a connector coupled to the flash memorycontroller is configured to have a plurality of lanes, a first portionof the lanes correspond to the first host, a second portion of the lanescorrespond to the second host; and if the first host is selected, thefirst portion of the lanes are enabled, and the second portion of thelanes are not used by the microprocessor to communicate with the firsthost; and if the second host is selected, the second portion of thelanes are enabled, and the first portion of the lanes are not used bythe microprocessor to communicate with the first host.
 7. The flashmemory controller of claim 6, wherein initially the flash memorycontroller communicates with the first host, and when the microprocessorreceives the selection signal indicating that the second host isselected, the microprocessor executes a lane reversal operation toreverse lane numbers of the lanes, and second portion of the lanes areenabled, and the first portion of the lanes are disabled.
 8. The flashmemory controller of claim 7, wherein when the microprocessor receivesthe selection signal indicating that the second host is selected, themicroprocessor executes the lane reversal operation to reverse the lanenumbers of the lanes, and the microprocessor enables the second portionof the lanes, and disables the first portion of the lanes.